Semiconductors: Silicon Sovereignty & India Semiconductor Mission

1. INDIA SEMICONDUCTOR MISSION (ISM) & SILICON FABS

Cue Words	Notes
Unified Policy Architecture	Launched under MeitY to coordinate fiscal incentives; ISM offers a flat **50% central capital subsidy**, matched with state-level incentives, to attract global semiconductor foundries to India. **Sovereign Incentive Outlay**: ₹76,000 Crore (~$10 Billion) under ISM 1.0, including a dedicated **₹1,000 Crore Design-Linked Incentive (DLI)** budget (50% of eligible design spend, up to ₹15 Crore/startup) and 100%-subsidised cloud access to EDA tools (Synopsys, Cadence) for registered design startups. **Import Dependence Baseline**: India imported **$18 Billion** of semiconductor chips in FY24 against a global chip market of ~$600 Billion (projected to cross $1 Trillion by 2030); domestic electronics demand is projected to reach **$300 Billion by 2026**. ISM targets training 85,000+ chip design/fabrication engineers.
Tata-PSMC Dholera Fab	India's first commercial silicon fab, a ₹91,000 Crore (~$11 Billion) joint venture with Taiwan's PSMC in Dholera, Gujarat, targeting **50,000 wafer starts per month** on mature nodes (28nm, 50nm, 90nm) — the workhorse nodes for automotive, industrial-power, and consumer-appliance chips. **First-Silicon Timeline**: Union Minister Ashwini Vaishnaw has confirmed a target of **December 2026** for first silicon output from the Dholera fab.
Strategic De-risking	Establishing domestic fab capacity reduces India's reliance on East Asian geopolitical choke points (Taiwan Strait tensions, South China Sea shipping lanes), securing a more resilient domestic silicon supply chain.
First AI-Enabled Chip Fab Notified as SEZ (Apr 2026)	2026 - India's first AI-enabled semiconductor fabrication plant — **Tata Semiconductor Manufacturing Pvt Ltd, Dholera, Gujarat** — notified as an SEZ on **9 April 2026**: spread over **66.166 hectares**, ₹91,000 crore investment, **21,000 jobs**. 2026 Enabled by **SEZ Rules 2006 amendments (3 June 2025)** that cut the minimum land requirement for semiconductor SEZs from **50 to 10 hectares**. 2026 Other approved semiconductor SEZs under this policy: **Micron Semiconductor** (Sanand, Gujarat, ₹13,000 crore, Assembly-Testing-Marking-Packaging unit), **CG Semi Pvt Ltd**, **Kaynes Semicon Pvt Ltd**, **Hubballi Durable Goods Cluster**.

> **Summary**: ISM's 50% capital-subsidy architecture has converted policy intent into physical construction — the Tata-PSMC Dholera fab is on track for first silicon by December 2026 — directly advancing India's strategic goal of de-risking chip supply from East Asian choke points.

2. BACKEND PACKAGING (ATMP/OSAT) & DESIGN TALENT

Cue Words	Notes
ATMP/OSAT Beachhead	Backend packaging and testing is less capital-intensive than front-end fabrication, making it a faster entry point. **Micron's Sanand, Gujarat** unit ($2.75 Billion / ₹22,500 Crore) was India's first major packaging beachhead. **Tata Assembly & Test, Jagiroad (Assam)**: Now operational, with capacity to package up to 48 million chips per day — a second major OSAT node alongside Sanand. **Bhiwadi, Rajasthan ATMP/OSAT**: Inaugurated May 2026 under the SPECS scheme, further diversifying India's backend-packaging geography. CG Power's Sanand OSAT (₹7,600 Crore, with Renesas Japan) is a further packaging node. **Fab Cleanroom & Wafer Specs**: Commercial fabs (e.g., Dholera) target **300 mm (12-inch) wafers** on ISO Class 1-3 cleanrooms (<10 particles >0.1μm per cubic foot), fabricating legacy/power-management chips at 28nm/40nm/90nm nodes. The legacy **SCL Mohali** facility (180nm line, serving defense/ISRO) has a proposed **$1 Billion** modernisation to reach 28nm.
VLSI Design Dominance	India houses nearly 20% of the global VLSI chip-design workforce (~1.25 Lakh designers). The Design Linked Incentive (DLI) scheme subsidises domestic chip-design startups to build and license indigenous intellectual property.

> **Summary**: India is building the backend (packaging/testing) layer faster than front-end fabrication — Sanand, Jagiroad, and Bhiwadi are now operational or under construction — while its pre-existing VLSI design strength (20% of global talent) is being converted into IP ownership via the DLI scheme.

3. ISM 2.0, ECOSYSTEM EXPANSION & INFRASTRUCTURAL CHALLENGES

Cue Words	Notes
ISM 2.0 & Ecosystem Depth (Budget 2026-27)	The 2026-27 Budget launched **ISM 2.0**, extending funding beyond fabs and OSAT into equipment, specialty materials, chemical supply chains, and workforce skilling — addressing the ecosystem gaps exposed by ISM 1.0. As of mid-2026, **13 approved semiconductor projects** are operational or under development across six states, with cumulative committed investment of roughly **₹1.64 Lakh Crore**. 2026 **ISM 2.0 mandate (Budget 2026-27)**: to produce equipment and materials, design **full-stack Indian IP**, and fortify supply chains — with explicit focus on **industry-led research and training centres**, alongside new safe-harbour provisions for IT/ITeS (higher threshold, competitive margin) supporting the broader tech-services ecosystem. 2026 **ECMS outlay increased to ₹40,000 Crore** in Budget 2026-27 — a Budget-level increase layered on top of the earlier tranche-wise approvals (see Section 6 below).
Market Growth Trajectory	Domestic semiconductor demand, valued at ~$27 Billion, is projected to reach $110 Billion by 2030 (roughly 10% of projected global demand) — the scale justifying continued ISM investment.
Infrastructural & Yield Challenges	**Resource Intensity**: A standard fab consumes 2-3 Million gallons of ultra-pure water daily and continuous power equivalent to a city of 100,000 people; sub-second voltage sags can ruin an entire wafer batch. **Supply-Chain Gaps**: India lacks domestic production of ultra-pure specialty chemicals, gases, photoresists, and silicon-wafer substrates — a gap ISM 2.0 explicitly targets. **The Yield Curve**: Commercial viability hinges on raising manufacturing yield (share of non-defective chips per wafer), which requires nanometre-level precision and deep specialised engineering expertise still being built domestically.
Two More ISM Units Approved (Cabinet, 5 May 2026)	2026 Cabinet approved **two more semiconductor manufacturing units** under ISM: **Crystal Matrix Limited (Dholera, Gujarat)** — India's **first commercial GaN (Gallium Nitride)-based Mini/Micro-LED display facility** plus a **GaN foundry** offering epitaxy on **6-inch wafers**; and **Suchi Semicon Private Limited (Surat, Gujarat)** — an **OSAT (Outsourced Semiconductor Assembly and Test) facility for discrete semiconductors**, capacity **1,033.2 million chips per annum**. **Combined investment ~₹3,936 crore**, generating **2,230 jobs**. With these approvals, **total ISM-approved projects reached 12**, with **cumulative investment of approximately ₹1.64 lakh crore**. **Design infrastructure support extended to 315 academic institutions and 104 startups**. **2 of the approved projects have already begun commercial shipments** from India; **2 more are expected to start soon**.

> **Summary**: ISM 2.0 marks a shift from "build the fab" to "build the ecosystem" — chasing the materials, chemicals, and equipment supply chain that ISM 1.0 left exposed — even as the fundamental infrastructural (water, power) and yield-curve challenges of fabrication remain unresolved.

3A. SEMICON 2.0: CABINET APPROVAL (15 JULY 2026) 2026

Cue Words	Notes
Semicon 2.0 outlay and six pillars	Cabinet approved **Semicon 2.0** on **15 July 2026**, with a **₹1,27,500 crore outlay**, building on the original Semicon 1.0/India Semiconductor Mission. **Six pillars**: (1) **Design** — chip/system IPs, building on 105 startups already designing chips; (2) **Machines & materials** — incentivizing manufacturers of semiconductor equipment, chemicals, and gases; (3) **More fabs** — attracting silicon, compound-semiconductor, discrete-component, and display fabs (India's **first fab scheduled for commissioning in 2028**); (4) Strengthening the **ATMP/OSAT** (packaging/testing) industry; (5) **R&D** — advancing beyond the current **28nm-110nm** process nodes; (6) **Talent development** — **315 universities** already training students on industry-standard **EDA (Electronic Design Automation)** tools, with **~68,000 students trained so far**.
ISM 1.0 progress snapshot at time of Semicon 2.0 announcement	**12 manufacturing units approved** with **₹1.64 lakh crore** cumulative investment (including 1 Silicon fab, 1 Silicon Carbide fab, 1 GaN Micro-LED display fab, and 9 packaging units). **3 companies** (Micron, Kaynes, CG Semi) have started **commercial production**; **24 chip-design projects** approved for financial support; **105 startups/MSMEs** granted access to industry EDA tools.

> **Summary**: Semicon 2.0's ₹1.27 lakh crore outlay and six-pillar structure (design, equipment/materials, more fabs, ATMP/OSAT, R&D beyond 28-110nm, talent) marks the next-phase policy layered on ISM 1.0's 12-project, ₹1.64 lakh crore base — pushing India from "first fab" toward a deeper, equipment-and-materials-level semiconductor ecosystem.

4. SEMICON INDIA CONFERENCE 2025 & TALENT ADVANTAGE

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Notes

Semicon India Conference 2025

PM described semiconductors as "digital diamonds" — elevating chip manufacturing to national strategic asset status equivalent to previous eras' agricultural and mineral resources. **10 large chip manufacturing/assembly facilities approved** across 6 States (Gujarat, Punjab, Uttar Pradesh, Assam, Odisha, Andhra Pradesh) — geographic diversification strategy to reduce concentration risk. **Talent Advantage**: One-fifth of global chip designers based in India — a pre-existing institutional advantage that ISM and Chips-to-Startup schemes aim to retain/expand domestically rather than exporting design talent to US/Taiwan. **Subsidy-Driven Ecosystem**: Foundries and assembly facilities receive up to **50% subsidy on setup costs**; Production-Linked Incentive (PLI) schemes further subsidise assembly of phones, PCs, and hardware — multi-layered fiscal incentive architecture. **Semicon India Conference Rotation**: 2022 Bengaluru (Inaugural), 2023 Gandhinagar Gujarat, 2024 Greater Noida UP, 2025-26 New Delhi (Yashobhoomi venue) — institutional visibility strategy.

> **Summary**: Semicon India 2025 reinforced positioning of semiconductors as core national economic priority; India's existing design-talent base (one-fifth global) is the key competitive lever if manufacturing fabs can anchor production domestically.

4A. MOBILE PHONE MANUFACTURING SCHEME (MPMS) — CABINET APPROVAL (15 JULY 2026) 2026

Cue Words	Notes
MPMS outlay, tenure and incentive structure	Cabinet approved the **Mobile Phone Manufacturing Scheme (MPMS)** on **15 July 2026** (same day as Semicon 2.0), with a **₹62,500 crore outlay** over a **5-year tenure (FY2026-27 to FY2030-31)** — succeeding the **PLI Scheme for Large Scale Electronics Manufacturing (PLI-LSEM)**, which ended **31 March 2026** (referenced as the "PLI schemes" subsidising phone assembly in Section 4 above). **Incentive structure**: **2.25% to 5%** on eligible sales (differentiated rates), plus up to an additional **1.5%** linked to domestic sourcing of components/sub-assemblies, plus an additional **3%** incentive on eligible sales for Indian-brand design and R&D.
Expected outcomes and sectoral context	Expected outcomes: cumulative mobile phone production of ~₹39,00,000 crore over the scheme's tenure, and ~60,000 direct jobs. India is now the world's second-largest mobile phone manufacturer by volume, with 99.2% of mobile phones used domestically manufactured in India; smartphones became India's single largest exported product category in 2025 (surpassing diesel fuel and cut diamonds). Electronics manufacturing has grown 7x and exports 11x since FY2014-15 under the Make in India initiative.

> **Summary**: MPMS replaces the expired PLI-LSEM with a differentiated, sourcing- and R&D-linked incentive structure (₹62,500 crore/5 years), aiming to consolidate India's position as the world's second-largest mobile manufacturer and its newly-dominant smartphone export category.

5. DISPLAY DRIVER CHIP MANUFACTURING (JEWAR, UP)

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Notes

HCL-Foxconn Joint Venture

Cabinet approved a **display driver chip manufacturing unit in Jewar, Uttar Pradesh**, a joint venture between **HCL (India) and Foxconn (Taiwan)** — bringing Taiwan's packaging expertise into India's domestic fab ecosystem. **6th ISM Phase 1 Unit**: First semiconductor plant in UP; expected to meet ~40% of India's display driver chip demand — a strategic chokepoint product where India currently fully imports. **Market Implication**: Display driver chip production domestically could enable establishment of a downstream display-panel manufacturing ecosystem within India.

> **Summary**: HCL-Foxconn Jewar joint venture addresses a specific strategic gap (display drivers) while also testing international equity partnerships within ISM's capital-subsidy framework — a model that could scale to other product verticals.

6. ELECTRONICS COMPONENTS MANUFACTURING SCHEME (ECMS)

Cue Words	Notes
ECMS Cabinet Approval (28 March 2025)	2025 - Cabinet approved the **Electronics Component Manufacturing Scheme (ECMS)** on **28 March 2025** — government funding of **₹22,919 crore**, expected to attract **₹59,350 crore** in investment and result in **₹4,56,500 crore** worth of production, generating **91,600 additional direct jobs**. 2025 **Scheme tenure**: 6 years (with a 1-year gestation period). 2025 **Target segments**: display module and camera module sub-assemblies (turnover-linked incentive); non-SMD passive components, electro-mechanicals, multi-layer PCBs, Li-ion cells, mobile/IT-hardware enclosures (turnover-linked incentive); HDI/MSAP/flexible PCB and SMD passive components (hybrid incentive); supply-chain/capital-equipment components (capex incentive). 2025 **Context**: India's electronics production grew from **₹1.90 lakh crore (FY2014-15)** to **₹9.52 lakh crore (FY2023-24)** — a CAGR of over **17%**; electronics exports grew from **₹0.38 lakh crore** to **₹2.41 lakh crore** over the same period — a CAGR of over **20%**.
ECMS Expansion & Budget 2026	Launched 2025 for 6-year period; offers output and employment-linked incentives to approved applicants. **Budget 2026 Expansion**: Increased outlay to **₹40,000 Crore** — triple the original semiconductor-fab-focused ISM 1.0, reflecting ecosystem-depth strategy. **Application Trends**: Received applications exceeding Cabinet targets; "Electro-mechanicals" and "multi-layer PCBs" attracted highest number of applications — highest-volume sub-sectors of electronics value chain. **Value Addition Focus**: Scheme aims to deepen India's electronics value chain beyond finished goods and fabs — targeting passive components and sub-assemblies (display controllers, camera modules), bare components (circuit boards, hardware enclosures, lithium-ion batteries). **Active vs Passive Components**: Active components (semiconductors, critical elements) distinguished from passive/sub-assembly manufacturing for differentiated incentive treatment.
ECMS 3rd Tranche Approval	2026 **3rd Tranche**: Government approved **22 more proposals** under ECMS's 3rd tranche, following an earlier approval of **24 applications worth ₹12,704 Crore**. Projected **investment of ₹41,863 Crore**, projected **production of ₹2,58,152 Crore**, and expected generation of **33,791 direct jobs**. Covers **11 target product segments** spanning mobile manufacturing, telecom, consumer electronics, strategic electronics, automotive, and IT hardware — confirming ECMS's remit is electronic *components* broadly, not chips/fabs alone (that remains ISM's domain).
Semicon India Programme — Cumulative Progress (PIB, 4 Feb 2026)	2026 - The Semicon India Programme (total outlay ₹76,000 Crore) has approved 10 projects with envisaged investments of about ₹1.6 lakh Crore — a cumulative-progress figure reported by MeitY distinct from the mid-2026 "13 approved projects, ₹1.64 lakh Crore" figure cited in Section 3 above (different reporting dates/counting basis). India's IT sector revenue rose to USD 283 Billion — cited alongside Semicon India progress as evidence of the broader electronics/IT ecosystem's scale-up.

> **Summary**: ECMS represents intentional ecosystem-deepening strategy — moving beyond capital-intensive fabs into smaller high-volume components, passive sub-assemblies, and battery packs, where India already has some indigenous manufacturing base; the Semicon India Programme's ₹76,000 Crore outlay and 10 approved projects (₹1.6 lakh Crore) alongside a $283 Billion IT sector show the fab and services layers scaling in parallel.

7. INDIGENOUS MICROPROCESSORS (DHRUV64, THEJAS, SHAKTI)

Cue Words	Notes
DHRUV64 Microprocessor Launch	MEITY announced launch of DHRUV64, an indigenous 64-bit, dual-core processor running at 1 GHz, developed by C-DAC under MEITY's Microprocessor Development Programme. Capable of running full operating systems — a capability gap in earlier indigenous processors. Part of broader ecosystem including SHAKTI, AJIT, VIKRAM, and THEJAS64 processors — diversifying India's processor portfolio across architectures.
RISC-V & Digital India RISC-V (DIR-V) Program	**RISC-V** is an open instruction-set architecture allowing chip design without paying licensing fees to proprietary (ARM, Intel) instruction-set gatekeepers — a strategic path to processor independence. RISC-V is **modular**, allowing designers to add features based on use-case needs rather than dictated by licensed-architecture constraints. **DIR-V Program**: THEJAS32 (first), THEJAS64 (second), DHRUV64 (third) DIR-V chips; next planned chips **DHANUSH** and **DHANUSH+** — systematic scaling of indigenous processor development. **Vikram 320I**: India's first fully indigenous **space-grade 32-bit microprocessor**, designed by ISRO (VSSC) and fabricated at Semiconductor Laboratory (SCL), Chandigarh — defense/space application specialized design.
C2S Chips-to-Startup Program	Aims to train 85,000 engineers in VLSI and embedded design over 5 years — scaling the talent pipeline for indigenous processor ecosystem. Linked to Design Linked Incentive scheme and INUP-i2i initiative for startup support.

> **Summary**: Dual strategy of indigenous processor development (DHRUV64, THEJAS series) using open-source RISC-V architecture + massive VLSI talent pipeline expansion (C2S) positions India to graduate from chip-design services to processor-architecture innovation.

8. ICEA-GSA COLLABORATION & GLOBAL VALUE CHAIN INTEGRATION

Cue Words	Notes
India Cellular & Electronics Association (ICEA)	**Apex industry body** representing India's electronics manufacturing ecosystem; plays major role in policy advocacy, establishing Centres of Excellence. Driving schemes like **Phased Manufacturing Program** and **Production Linked Incentive** to position India as global manufacturing and export hub. Vision: Build **$300 Billion electronics manufacturing ecosystem by 2025-26**.
Global Semiconductor Alliance (GSA) Partnership	**ICEA-GSA Strategic Collaboration**: Aimed at accelerating India's integration into **global semiconductor value chain**. **GSA Profile**: Global organisation connecting entire semiconductor ecosystem; provides neutral platform for industry leaders to network, share market intelligence, address supply-chain challenges. **Market Representation**: GSA represents over **80% of the $620 Billion global semiconductor industry** — access to a pre-existing global network essential for India's fab/component ecosystem to integrate with established buyer relationships.

> **Summary**: ICEA-GSA collaboration is intentional ecosystem-weaving — linking India's domestic semiconductor policy (ISM, ECMS) to global value chains and buyer networks, reducing the risk of India building isolated fab capacity without downstream demand.

UPSC Mains PYQs

• Semiconductor Manufacturing & ISM: "The semiconductor industry is the backbone of modern electronics, yet India has traditionally been fully reliant on imports." Analyze the strategic and economic significance of the India Semiconductor Mission (ISM). Discuss the challenges in establishing high-tech silicon fabrication facilities in India. (15 Marks, 250 Words)
• Display Drivers & Strategic Gaps: Critically examine India's decision to prioritize display driver chip manufacturing (Jewar facility) as a first ISM project. What gaps in India's downstream electronics ecosystem does this address?